The present method relates generally to methods for forming vias, i.e., contacts, in semiconductor devices. More specifically, the invention relates to methods for forming vias in high density integrated circuits.
In the manufacture of integrated circuits, at least one wiring level that connects individual components of the circuit, usually MOS transistors, to one another is formed after the fabrication of the individual components.
In conventional technologies, a relatively thick insulating layer, usually composed of silicon oxide with additives, is deposited for that purpose. Via holes are anisotropically etched through this insulating layer, i.e., with vertical privileged direction, with the assistance of a photoresist mask, down to the contacting regions of the components. Included among these contacting regions are gates and doped regions of the transistors.
To make the contacts, a metallization is deposited, for example an A1SiCu alloy. The metallization fills up the via holes and forms a continuous layer at the surface of the insulating layer. This continuous layer then is structured to provide the finished wiring level.
In this process, the via holes must be placed such that a clearance distance is assured between the location of the via hole and neighboring, conductive regions in or at the surface of the substrate. Particularly when contacting doped regions of a MOS transistor, a clearance distance to neighboring gate electrodes must be assured in order to avoid shorts. This clearance distance must be of such a size that it is sure to intercept the unavoidable process and alignment tolerances. Yet, this clearance distance causes a loss in space that is especially detrimental in miniaturized, integrated circuits having extremely high packing densities, for example, dynamic random access memories, DRAMs.
Methods that address this disadvantage are known from literature in the relevant art.
K H. Kuesters, et al., Sympos. on VLSI Technology, 1987 Tech. Digest, pages 93 ff, incorporated herein by reference, discloses that the gate electrodes can be enveloped with an insulating cover layer and insulating side wall coverings, what are referred to as spacers, before the deposition of the thick, insulating layer. Subsequently, a thin auxiliary layer of, for example, silicon nitride is deposited. After this, the thick insulating layer in which the via holes are opened is deposited. The auxiliary layer thereby acts as an etch stop. The auxiliary layer in the opened via holes is subsequently selectively etched off relative to the substrate and relative to the insulation enveloping the gate electrodes. In this method, the via holes can be placed overlapping relative to the gate electrodes. A high etching selectivity of silicon nitride relative to the insulation enveloping the gate electrodes, usually silicon oxide, is required in this method.
Another method is disclosed in K. H. Kuesters, et al., ESSDERC 1988, Journal de Physique, pages 503 ff, incorporated herein by reference, which can be utilized given inadequate etching selectivity of silicon nitride to oxide. In this method, a thin layer of polysilicon is additionally deposited over the auxiliary layer of silicon nitride. After the via holes are etched through the thick insulating layer--the thin polysilicon layer acting as etch stop therein--the polysilicon is first selectively etched relative to silicon nitride and the silicon nitride is then selectively etched relative to the substrate. Outside the contact regions, the polysilicon layer remaining under the insulating layer is later oxidized by suitable tempering in an O.sub.2 atmosphere. But, this process step is extremely problematical.
Auxiliary layers that must in turn be completely removed in the via hole region are utilized in both of these known methods.
It is fundamentally impossible in the two known methods to simultaneously open via holes to doped regions in the substrate, source/drain regions, and to gate electrodes of polysilicon. The via holes to the gate electrodes must be opened after the silicon nitride etching.